In operation, an integrated circuit formed at a die, also referred to as a chip, generates heat. The heat generated can be unevenly distributed across the chip. Such uneven heat distribution can be evidenced by a large temperature difference between different portions of the chip, or by a large temperature gradient at various portions of the chip. The operating characteristics of the devices implemented on a particular chip may be sensitive to differences in temperature, such that a device that is implemented in a relatively hotter portion of the chip may perform differently than an identically laid out copy of the device that is implemented in a relatively cooler portion of the chip. Such differences in performance may necessitate design criteria that include wide tolerances for such characteristics as circuit timings or power delivery. Moreover, large temperature gradients in the chip may result in large mechanical stresses within the chip or within attachment mechanisms between the chip and an associated chip carrier, resulting in premature device failure. The problems associated with large temperature differences and large temperature gradients in a chip are compounded when two or more chips are stacked together into a three-dimensional (3D) array.
There is therefore a need to provide more even temperatures and for lower temperature gradients across a chip or within a 3D array of chips.
The use of the same reference symbols in different drawings indicates similar or identical items.